View ISL6224CA_706458.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL6224
Data Sheet December 28, 2004 FN9042.7
Single Output Mobile-Friendly PWM Controller
The ISL6224 provides power control and protection for a single, adjustable output voltage required to power chip-sets and memory banks in high-performance notebooks and PDAs. This output voltage is adjustable in the range from 0.9-5.5V. The hysteretic or PWM controller regulates the output voltage from battery voltages ranging from 4V to 24V. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of input voltages and loads. Efficiency is even further enhanced by using MOSFET's rDS(ON) as a current sense component. Feed-forward ramp modulation, average current mode control and internal feed-back compensation provide fast and firm handling of transients when powering advanced chip sets. Two-stage conversion using system 5V voltage is possible at a higher frequency (600kHz) to minimize the output filter size. The ISL6224 monitors the output voltage. A PGOOD (power good) signal is issued when soft-start is completed and the output is within 10% of the set point. A built-in overvoltage protection prevents output voltage from going above 120% of the set point. Undervoltage protection latches the chip off when the output drops below 70% of its setting value after soft-start sequence is completed. The PWM controller's overcurrent circuitry monitors the output current by sensing the voltage drop across the lower MOSFET. If higher precision sense technique is required, an optional external current-sense resistor may be used.
Features
* Adjustable output voltgage: 0.9-5.5V * High efficiency over wide load range - Higher efficiency in hysteretic mode at light load * Lossless current sense scheme - Uses MOSFET's rDS(ON) - Optional current sense method higher precision * Supply operation mode - Wide VIN range: 4V-24V - Single 5V system rail * Input undervoltage lock-out on VCC pin(UVLO) * Excellent dynamic response - Combined voltage feed-forward and current mode control * Power-Good indicator * 300/600kHz switching frequency * Thermal shut-down * Pb-Free Available (RoHS Compliant)
Applications
* Mobile PCs * Graphic cards * Hand-held portable instruments
Related Literature
* Application Note AN9983
Ordering Information
PART NUMBER ISL6224CA ISL6224CAZ (Note 1) ISL6224CAZA (Note 1) NOTE: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-T" for Tape and Reel. TEMP. (C) -10 to 85 -10 to 85 -10 to 85 PACKAGE 16 Ld SSOP 16 Ld SSOP (Pb-free) 16 Ld SSOP (Pb-free) PKG. DWG. # M16.15A M16.15A M16.15A
Pinout
ISL6224 (SSOP) TOP VIEW
VIN PGOOD EN OCSET VOUT VSEN SOFT GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FCCM BOOT UGATE PHASE ISEN VCC LGATE PGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6224
Absolute Maximum Ratings
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V Phase and Isen Pins . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +29.0V BOOT and Ugate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 32.0V BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 15V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SSOP - Lead Tips Only)
Recommended Operating Conditions
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V 5% Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to +24.0V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-10C to 85C Junction Temperature Range. . . . . . . . . . . . . . . . . . .-10C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY Bias Current Shutdown Current VCC UVLO Rising Vcc Threshold Falling Vcc Threshold Vcc UVLO Hysteris VIN Input Voltage Pin Current (Sink) Input Voltage Pin Current (Source) Shutdown Current OSCILLATOR PWM Oscillator Frequency PWM Oscillator Frequency Ramp Amplitude, pk-pk Ramp Amplitude, pk-pk Ramp Offset REFERENCE AND SOFT-START Internal Reference Voltage Reference Voltage Accuracy Soft-Start Current During Start-up Soft-Start Threshold PWM CONVERTER Load Regulation VSEN pin bias current
Operating Conditions: VCC = 5V, TA = 10C to 85C, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC ICCSN
LGATE, UGATE Open, VSEN forced above regulation point
-
850 5
1300 15
A A
4.3 4.1 0.1
-
4.75 4.5 0.5
V V V
IVIN IVIN IVIN
VIN pin connected to the input voltage source VIN pin connected to ground
10 -7 -
20 -15 -
30 -20 1
A A A
Fc1 Fc2 VR1 VR2 VROFF
VIN = 3.5V - 24V VIN 0.5V VIN = 16V, By Design VIN 5V, By Design
255 510 -
300 600 2 1.25 0.5
345 690 -
kHz kHz V V V
VREF
-1.0
0.9 5 1.5
+1.0 -
V % A V
ISOFT VSOFT
-
0.0mA < IVOUT1 < 3.0A; 5.0V < VIN < 24.0V IVSEN
-1.0 -
80
+1.0 -
% nA
2
FN9042.7 December 28, 2004
ISL6224
Electrical Specifications
PARAMETER VOUT pin input impedance Undervoltage Shutdown Level Overvoltage Protection PWM CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance POWER GOOD AND CONTROL FUNCTIONS Power-Good Lower Threshold Power-Good Higher Threshold PGOOD Leakage Current PGOOD Voltage Low EN - Low (Off) EN - High (On) FCCM -Hysteretic Operation Enabled VPGVPG+ IPGLKG Fraction of the set point; ~3s noise filter Fraction of the set point; ~3s noise filter VPULLUP = 5.5V IPGOOD = -4mA -14 10 2.0 Vcc/2 -8 15 1 0.5 0.8 % % A V V V V R2UGPUP R2UGPDN R2LGPUP R2LGPDN 8 3.2 8 1.5 15 5 15 2.4 Operating Conditions: VCC = 5V, TA = 10C to 85C, Unless Otherwise Noted. (Continued) SYMBOL IVOUT VUV1 VOVP1 Fraction of the set point; ~3s noise filter Fraction of the set point; ~1s noise filter TEST CONDITIONS MIN 40 70 113 TYP 55 MAX 65 80 120 UNITS k % %
3
FN9042.7 December 28, 2004
Functional Block Diagram
FCCM VIN VCC GND HGDR1 HI PHASE BOOT UGATE
FCCM FSET CLK RAMP POWER-ON RESET (POR) GATE LOGIC POR DEADT PWM/HYST POR EN SDWN REFERENCE AND SOFT SOFT-START REF PWM ON HYST ON SHUTOFF
OUTPUT VOLTAGE MONITOR
+
VOLTSECOND CLAMP FFBK LGATE1
REF + -
-+
4
FN9042.7 December 28, 2004
CLK
GATE CONTROL VCC LGDR LO OVP HYST COMP1 + OC COMP1 EA1 CLK1 LGATE PGND
ISL6224
PWM LATCH 1 VCC QD R Q<
OC LOGIC1
+
+ R1=20K + LGATE ISEN VSEN
MODE CHANGE COMP
PGOOD
PWM/HYS
LOGIC OCSET VOUT
ISL6224 Functional Pin Description
VIN (Pin 1)
Provides battery voltage to the oscillator for feed-forward rejection of the input voltage variation. Also, this pin programs frequency of the internal clock and gain of the ramp generator. When connected to the battery, which voltage varies from 4V to 24V, the clock frequency is set to 300kHz and the ramp gain is set accordingly to accommodate the wide input voltage range. For two step conversion from the system 5V power rail, the Vin pin is connected to ground via a 150k resistor. This arrangement changes the gain of the ramp generator to accommodate the lower input voltage but does not change the clock frequency. When the Vin pin is connected to ground, the clock frequency is set to 600kHz. The ramp generator gain is also changed accordingly. This circuit arrangement enables the designer to choose smaller output filter components.
GND (Pin 8)
Signal ground for the IC.
PGND (Pin 9)
This is the power ground connection for PWM converter. This pin is connected to the lower MOSFET's source terminal.
LGATE (Pin 10)
This pin provides the gate drive for the lower MOSFET.
VCC (Pin 11)
This pin provides power to the chip.
ISEN (Pin 12)
This pin is used to monitor the voltage drop across the lower MOSFET for current feedback and overcurrent protection. For precise current detection this input can be connected to an optional current sense resistor placed in series with the source of the lower MOSFET.
PGOOD (Pin 2)
PGOOD is an open collector output used to indicate the status of the output voltage. This pin is pulled high when the system output is within 10% of its respective nominal voltage.
PHASE (Pin 13)
Connect this pin to the PHASE node of the converter. The PHASE node is the junction point of the upper MOSFET source, output filter inductor, and lower MOSFET drain.
UGATE (Pin 14)
This pin provides the gate drive for the upper MOSFET.
EN (Pin 3)
This pin provides the enable/disable function for the chip. The IC is enabled when this pin is pulled over 2V or left open. Note: a pulldown resistance of 100k or less is required to disable the controller.
BOOT (Pin 15)
This pin powers the upper MOSFET drivers of the PWM converter. Connect this pin to the junction of bootstrap capacitor with the cathode of the bootstrap diode. Anode of the bootstrap diode is connected to the VCC pin.
OCSET (Pin 4)
A resistor from this pin to GND sets the overcurrent protection threshold.
FCCM (Pin 16)
This pin, when pulled to VCC, restrains hysteretic operation in light loads.
VOUT (Pin 5)
This pin is used for feedback of the output voltage to properly position output voltage during operational mode change.
General Description
Operational Overview
The ISL6224 is a single-channel PWM controller intended for chipset, DRAM, or other low voltage power needs of modern notebook and sub-notebook PCs. The IC integrates control circuits and feedback compensation for a single synchronous buck converter. The output voltage is set in the range of 0.9-5.5V by an external resistive divider. The synchronous buck converter can be configured for either 300kHz or 600kHz switching frequencies. When operated from battery, a switching frequency of 300kHz is recommended. When operating from 5V, switching frequencies of 300kHz or 600kHz are an option. For 300kHz operation, pin 1 should be connected through a resistor (150K) to gnd. For 600kHz operation, pin 1 should simply be
VSEN (Pin 6)
This pin is connected to the output via a resistive divider and provides the voltage feedback signal for the PWM controller. The PGOOD, UVP, and OVP circuits use this signal to report output voltage status.
SOFT (Pin 7)
This pin provides soft-start of the PWM controller. When the EN pin is pulled high, the voltage on the capacitor connected to the soft-start pin is rising linearly due to the 5A pull-up current. The output voltage follows the voltage on the capacitor until it reaches the value of 0.9V. The further rise of the voltage on the soft-start capacitor does not affect the output voltage.
5
FN9042.7 December 28, 2004
ISL6224
grounded. Table 1. shows the configuration for different modes of operation. Figure 1 below shows plots of the ramp speed compensation.
300kHz CLOCK 600kHz CLOCK Vin t --------- --2T Vo/4 Vo/8 Vin ---------- t4T Vin t --------- --8T
of this resistor can be obtained from the following expression:
11 * Risen Rocset = --------------------------------Ioc * Rdson
FIGURE 1. RAMP SPEED COMPENSATION Vo = 2.5V
TABLE 1. CONFIGURATION FOR MODES OF OPERATION OPERATION One-stage 300kHz Two-stage 300kHz Two-stage 600kHz PIN 1 CONNECTION Vin 150K-GND GND PIN 1 POTENTIAL V1 > 4V 1V < V1 < 2V V1 < 0.5V
where Ioc is the value of overcurrent. The resulting current out of the ISEN pin through RISEN, is used for current feedback and current limit protection. This is compared with an internal current limit threshold. When a sampled value of the output current is determined to be above the current limit threshold, the PWM drive is terminated and a counter is initiated. This limits the inductor current build-up and essentially switches the converter into current-limit mode. If an overcurrent is detected between 26ms to 53ms later, an overcurrent shutdown is initiated. If during the 26ms to 53ms period, an overcurrent is not detected, the counter is reset and sampling continues as normal. This current limit scheme has proven to be very robust in applications like portable computers where fast inductor current build-up is common due to a large difference between input and output voltages and a low value of the inductor.
The synchronous converter light-load efficiency is enhanced by a hysteretic mode of operation which is automatically engaged at light loads when the inductor current becomes discontinuous. As the filter inductor resumes continuous current, the PWM mode of operation is automatically restored. The ISL6224 control IC employs an average current mode control scheme with input voltage feedforward ramp programming for better rejection of input voltage variations.
Light-Load (Hysteretic) Operation
In the light-load (hysteretic) mode the output voltage is regulated by the hysteretic comparator which regulates the output voltage by maintaining the output voltage ripple as shown in Figure 2. In hysteretic mode, the inductor current flows only when the output voltage reaches the lower limit of the hysteretic comparator and turns off at the upper limit. Hysteretic mode saves converter energy at light loads by supplying energy only at the time when the output voltage requires it. This mode conserves energy by reducing the power dissipation associated with continuous switching. During the time between inductor current pulses, both the upper and lower MOSFETs are turned off. This is referred to as `diode emulation mode' because the lower MOSFET performs the function of a diode. This diode emulation mode prevents the output capacitor from discharging through the lower MOSFET when the upper MOSFET is not conducting.
NOTE: the PWM only operation can intentionally be forced by tying pin 16, FCCM, to VCC.
Current Sensing and Current Limit Protection
The PWM converter uses the lower MOSFET on-state resistance, rDS(ON), as the current-sensing element. This technique eliminates the need for a current sense resistor and the associated power losses. If more accurate current protection is desired, current sense resistors may be used in series with the lower MOSFET's source. A current proportional signal is used to provide average current mode control and overcurrent protection. The gain in the current sense circuit is set by the resistor connected from ISEN (pin 12) to the PHASE node of the buck converter. The value of this resistor can be estimated by the following expression:
Iomax * Rdson Risen = ------------------------------------------ - 100 75A
where Iomax is the maximum inductor current. The value of RISEN should be specified for the expected maximum operating temperature. An overcurrent protection threshold is set by an external resistor connected from OCSET (pin 4) to ground. The value
6
FN9042.7 December 28, 2004
ISL6224
VOUT t
IL
t
due to the voltage drop on the output capacitor ESR. If the decrease causes the output voltage to drop below the hysteretic regulation level, the mode is changed to PWM on the next clock cycle. This insures the full power required by the increase in output current.
PHASE COMP 12345 678 MODE OF OPERATION PWM HYSTERETIC
t
IL
t
t
FIGURE 2. HYSTERETIC OPERATION MODE
Operation-Mode Control
The mode-control circuit changes the converter's mode of operation based on the voltage polarity of the phase node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the phase node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 3. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the `reverse' direction, the phase node becomes positive, and the mode is changed to hysteretic. A phase comparator handles the timing of the phase node voltage sensing. A low level on the phase comparator output indicates a negative phase voltage during the conduction time of the lower MOSFET. A high level on the phase comparator output indicates a positive phase voltage. When the phase node is positive (phase comparator high), at the end of the lower MOSFET conduction time, for eight consecutive clock cycles, the mode is changed to hysteretic as shown in Figure 3. The dashed lines indicate when the phase node goes positive and the phase comparator output goes high. The solid vertical lines at 1,2,...8 indicate the sampling time, of the phase comparator, to determine the polarity (sign) of the phase node. At the transition between PWM and hysteretic mode both the upper and lower MOSFETs are turned off. The phase node will `ring' based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output voltage. The mode change from hysteretic to PWM can be caused by one of two events. One event is the same mechanism that causes a PWM to hysteretic transition. But instead of looking for eight consecutive positive occurrences on the phase node, it is looking for eight consecutive negative occurrences on the phase node. The operation mode will be changed from hysteretic to PWM when these eight consecutive pulses occur. This transition technique prevents jitter of the operation mode at load levels close to boundary. The other mechanism for changing from hysteretic to PWM is due to a sudden increase in the output current. This step load causes an instantaneous decrease in the output voltage 7
FN9042.7 December 28, 2004
PHASE NODE 7 8
t 1 2 3 4 5 6
PHASE COMP MODE OF OPERATION PWM
t HYSTERETIC t
FIGURE 3. MODE CONTROL WAVEFORMS
Gate Control Logic
The gate control logic translates generated PWM control signals into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operational conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-tosource voltages of both upper and lower MOSFETs. The lower MOSFET is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through.
ISL6224
Soft-Start Operation
Soft-start of the Synchronous Buck Converter is accomplished by means of a capacitor connected from pin 7, SOFT to ground. The soft-start time can be obtained from the following equation:
1.5V x Css Tss = ----------------------------5.0A
This `soft-crowbar' and monitoring of the output, prevents the output voltage from ringing negative as the inductor current flows in the `reverse' direction through the lower MOSFET and output capacitors.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of the output capacitors is also dependent on the output inductor so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter's response to a load transient is the time required for the inductor current to slew to its new level. Given a sufficiently fast control loop design, the ISL6224 will provide either 0% or 94% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. If the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, this reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is:
I TRAN L O x I TRAN C OUT = --------------------------------------------- x -------------------( V IN - V OUT ) x 2 DV OUT
Figure 4 shows the soft-start initiated by the ENABLE pin being pulled high with the VIN input at 5.6V and the resulting 3.3V output and PGOOD signal. While the ENABLE pin is held low, prior to t0, the output is off. When the EN pin is pulled high, at t0, the voltage on the capacitor connected to the soft-start pin rises linearly due to the internal 5A current source starts charging the capacitor. The output voltage follows the voltage on the capacitor till it reaches the value of 0.9V at t1. At this moment, t1, the output voltage started regulation. The soft-start is complete when PGOOD pin is high at t2 and further rise of the voltage on the soft-start capacitor does not affect the output voltage.
t0
t1
t2
FIGURE 4. MODE CONTROL WAVEFORMS
Where: COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VOUT is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (equivalent series resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by:
V RIPPLE = I L x ESR
Power Good Status
The ISL6224 monitors the output voltage. A single powergood signal, PGOOD, is issued when soft-start is completed and the output is within 10% of it's set point. After the softstart sequence is completed, undervoltage protection latches the chip off when any of the monitored outputs drop below 70% of its set point. A `soft-crowbar' function is implemented for an overvoltage on the output. If the output voltage goes above 120% of its nominal output level, the upper MOSFET is turned off and the lower MOSFET is turned on. This `soft-crowbar' condition will be maintained until the output voltage returns to the regulation window and then normal operation will continue.
where, I L is calculated in the Inductor Selection section. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that
8
FN9042.7 December 28, 2004
ISL6224
could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications, at 300kHz, for the bulk capacitors. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. The stability requirement on the selection of the output capacitor is that the `ESR zero', fZ, be between 1.2kHz and 30kHz. This range is set by an internal, single compensation zero at 6kHz. The ESR zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. Therefore:
1 C OUT = ------------------------------------------2 x x ESR x f Z
Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON(R) series offer low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX is surge current tested.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. One dual N-Channel or two N-Channel MOSFETs are used in each of the synchronous rectified buck converters for the outputs. These MOSFETs should be selected based upon rDS(ON) , gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near-zero voltage.
I O x r DS ( ON ) x V OUT I O x V IN x t SW x F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 I O x r DS ( ON ) x ( V IN - V OUT ) P LOWER = -------------------------------------------------------------------------------V IN
2 2
In conclusion, the output capacitors must meet three criteria: 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current, and 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin.
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by the following equation:
V IN - V OUT V OUT I L = ------------------------------- x --------------FS x L V IN
where Fs is the switching frequency.
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. The AC RMS input current varies with load. Depending on the specifics of the input power and it's impedance, most (or all) of this current is supplied by the input capacitor(s).
The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6224 and do not heat the MOSFETs. However, a large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications.
9
OS-CON(R) is a registered trademark of Sanyo Electric Company, Ltd. (Japan) FN9042.7 December 28, 2004
ISL6224
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turn-off transition of one of the upper PWM MOSFETs. Prior to turn-off, the upper MOSFET is carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. See the Application Note AN9983 for the evaluation board component placement and the printed circuit board layout details. There are two sets of critical components in a DC/DC converter using an ISL6224 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes, but do not unnecessarily oversize these particular islands. Since the phase nodes are subjected to very high dV/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents.
Small Components Signal Layout Considerations
The Vin pin 1 input should be bypassed with a 1.0F capacitor. The bypass capacitors for Vin and the soft-start capacitor, should be located close to their connecting pins on the control IC. Refer to the Application Note AN9983 for a recommended component placement and interconnections. Figures 5, 6 and 7 show application circuits for the three modes of operation. Mode 1 is operating from battery voltage and operating at 300kHz switching frequency. Mode 2 is operating off of 5V and operating at 300kHz switching frequency. Mode 3 is operating off of 5V and operating at 600kHz switching frequency.
Power Components Layout Considerations
The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power MOSFETs. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. Insure the current paths from the input capacitors to the MOSFETs, to the output inductors and output capacitors are as short as possible with maximum allowable trace widths.
10
FN9042.7 December 28, 2004
ISL6224 ISL6224 DC-DC Converter Application Circuits
Figure 5 shows an application circuit of a DC/DC converter for a notebook PC. The power supply provides +V2_5S from either +4V-24VDC battery voltage or system +5V bus. For detailed information on the circuit, including a bill of materials and circuit board description, see Application Note AN9983. Also see Intersil's web site (http://www.intersil.com) for the latest information.
+5.6-24VIN C2 1F + C1 56F GND
+5.0VCC VIN R2 TBD 15 FCCM OCSET 4 1 11 VCC BOOT CR1 + C3 33F
16 ISL6224
14 13 12
UGATE PHASE ISEN Risen TBD
Q1 1/2 FDS6912A C6 0.1F L1 6.4H +V2_5S (3A) +
EN
3
SOFT C4 0.015F PGOOD
7
10 9
LGATE PGND VSEN VOUT
C5 330F Q2 2/2 FDS6912A
R3
C6
2 8 GND
6 5
R4
FIGURE 5. APPLICATION CIRCUIT FOR ONE-STEP CONVERSION (MODE 1)
11
FN9042.7 December 28, 2004
ISL6224
+5.0VCC + R2 TBD 15 FCCM OCSET 4 11 VCC BOOT CR1 C1 33F GND
Q1 1/2 FDS6912A C4 0.1F Risen TBD L1 6.4H +V2_5S (2A) + R3
16 ISL6224
14 13 12
UGATE PHASE ISEN
EN
3
SOFT C2 0.015F PGOOD
7
10 9
LGATE PGND VSEN VOUT
C5 330F Q2 2/2 FDS6912A
C6
2 8 GND 1 VIN R5
6 5
R4
FIGURE 6. APPLICATION CIRCUIT FOR TWO-STEP 300kHz CONVERSION (MODE 2)
+5.0VCC + R2 OCSET 4 VCC BOOT Q1 1/2 FDS6912A UGATE PHASE ISEN Risen TBD SOFT C2 0.015F PGOOD 7 10 9 2 8 GND 1 VIN 6 5 LGATE PGND VSEN VOUT R4 C5 330F Q2 2/2 FDS6912A + R3 C6 C4 0.1F L1 6.4H +V2_5S (2A) CR1 C1 33F GND
11 15
TBD
FCCM
16 ISL6224
14 13 12
EN
3
FIGURE 7. APPLICATION CIRCUIT FOR TWO-STEP 600kHz CONVERSION (MODE 3)
12
FN9042.7 December 28, 2004
ISL6224 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45 L GAUGE PLANE 0.25(0.010) M BM
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1 A2 B C D E
A2 C 0.10(0.004) C AM BS
MILLIMETERS MIN 1.55 0.102 1.40 0.20 0.191 4.80 3.81 5.84 0.25 0.41 16 8 0 8 MAX 1.73 0.249 1.55 0.31 0.249 4.98 3.99 6.20 0.41 0.89 NOTES 9 3 4 5 6 7 Rev. 2 6/04
MIN 0.061 0.004 0.055 0.008 0.0075 0.189 0.150 0.230 0.010 0.016 16 0
MAX 0.068 0.0098 0.061 0.012 0.0098 0.196 0.157 0.244 0.016 0.035
e
B 0.17(0.007) M
A1
e H h L N
0.025 BSC
0.635 BSC
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN9042.7 December 28, 2004

▲Up To Search▲

Price & Availability of ISL6224CA

	To Download ISL6224CA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .